The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this disclosure and are not admitted to be prior art by inclusion in this section.
In the semiconductor wafer-fabrication industry, mask layout teams responsible for designing photolithography masks implement design rule sets. The design rule sets ensure that features rendered on a photolithography mask are correct so that corresponding features of an integrated circuit (IC) die, fabricated using patterns exposed via the photolithography mask, are correct in terms of dimensions and tolerances when manufactured as part of a photolithography process. Although multiple semiconductor wafer-fabrication facilities may manufacture wafers containing multiple IC die, each semiconductor-wafer fabrication facility may require a “tailored” mask set that accounts for variations and process capabilities of a group of semiconductor-wafer manufacturing tools at that semiconductor-wafer fabrication facility. Tailoring mask sets for each semiconductor-wafer fabrication facility requires design rule sets that specify certain geometric restrictions of features rendered onto the mask set, thereby ensuring sufficient margin with respect to manufacturing tool process capabilities as well as compounding effects of tolerance stack-ups inherent to semiconductor-wafer fabrication processes.
Today, a layout engineer may design a mask using computer-aided drafting (CAD) software. It is common for such software to include design rule checking (DRC) operations that might highlight, to the mask layout engineer, that a feature he is designing violates one or more rules of a design rule set. Such a violation may be, for example, a violation in a feature width, a violation in a spacing associated with the feature, or a violation of a feature enclosure.
Design rule sets are becoming increasingly more complex with each subsequent generation of semiconductor wafer-fabrication process technology. In deep sub-100 nanometer (nm) process technologies, for example, there can be tens of thousands of design rules that need checking to ensure that a mask set, tailored for a particular semiconductor-wafer fabrication facility, will yield functional IC die. Furthermore, for each of the design rules, there may be one or more solutions that the mask layout team may implement to resolve a violation.
Thus, rule checking is a computationally intense task followed by tedious searching and review of available solutions that will resolve the violation. With the sheer volume of design rules, an experienced layout engineer may have difficulty understanding a rule of a design rule set. Furthermore, the layout engineer may experience difficulties matching a violation of the rule to one or more solutions available to obviate the violation, especially for variances in design rules for different semiconductor-wafer manufacturing facilities.